A significant barrier to improving the performance of a microprocessor system is the access time of system memory. Although the speed of semiconductor memories has improved over time, the speed of dynamic random access memory ("DRAM") devices has not kept pace with the speed of the processors. Consequently, when executing most applications, a processor will experience numerous wait states while system memory is accessed. A frequently employed solution to this problem is the incorporation in the microprocessor system of a high-speed cache memory comprising static random access memory ("SRAM") devices. In general, a cached system will experience significantly fewer wait states than a non-cached system.
The simplest form of cache is generally referred to as a direct-mapped cache, wherein contents of the system memory are retrieved and stored in cache locations having the same low-order address. For example, if an 8K cache is provided, the thirteen lowest order address bits of the system memory location to be retrieved define the cache storage location A significant disadvantage of a direct-mapped cache is that the cache contents will be overwritten whenever there is an access request to a system memory location having the same low order address but a different high order address.
To overcome this disadvantage, a set associative cache structure is sometimes used. For example, with a two-way set associative cache, the cache memory is physically divided into two banks of SRAMs. Thus, a two-way set associative 8K cache would comprise two 4K banks of SRAM. Data retrieved from system memory may be mapped into either one of the two banks since the two banks have identical low order addresses. A cache hit in one bank causes a least recently used (LRU) flag to be set for the corresponding address in the other bank. Thus, cache writes may be directed to the cache bank whose contents were least recently used, thereby preserving the more recently used data for subsequent accesses by the central processing unit ("CPU"). An associative cache significantly improves the cache hit rate and thus improves overall system performance.
Modern microprocessor systems have enormous virtual addressing capabilities. For example, the protected virtual mode of the Intel 386.TM.SX processor supports a virtual memory of 64 terabytes (2.sup.46 bytes). Management of such a large virtual address space is facilitated by an expanded memory system (EMS) such as specified in the Lotus/Intel/Microsoft (LIM) 4.0 standard. Under this standard, address space is partitioned into 16K byte pages that are mapped into the physical address space. Use of EMS complicates cache management since any changes to the EMS mapping will invalidate cached data. To preserve cache integrity, prior art systems must either make EMS pages non-cacheable and suffer a loss in system performance or flush the contents of the cache whenever an EMS mapping change invalidates the contents.
One of the objects of the present invention is to provide a cache controller that overcomes many of the prior art disadvantages of operating in an EMS environment.